1. Field of the Invention
This invention relates to a method and structure for depositing metal conductors on a substrate. In particular, a dual overhang, collimated metal process for depositing metal lines on a semiconductor chip is described.
2. Background Art
Current Very Large Scale Integrated (VLSI) circuits and Ultra Large Scale Integrated (ULSI) circuits require the deposition of metal interconnection lines less than one micron in width. Metal lift-off processes have been widely used for depositing narrow metal conductors in the prior art. The basic "lift-off" method is described in U.S. Pat. No. 2,559,389. Improvements to the basic lift-off method have been made, as for example in commonly assigned U.S. Pat. Nos. 3,849,136; 3,873,861 and 4,519,872.
The central concept of the lift-off method involves the deposition of a non-radiation sensitive lift-off layer, followed by the deposition of a thin-film of an inorganic material as a barrier layer. The desired metallurgy pattern is formed in a top resist layer using conventional lithographic techniques and etched into the barrier layer. The barrier layer functions as an etch barrier during subsequent reactive ion etching to form openings through the lift-off layer, extending to the substrate. Metal is then deposited, by sputtering or evaporation, for example. Following the metal deposition, immersion in a solvent dissolves or releases the base lift-off film, thereby leaving the metal conductors deposited in the windows.
One of the problems with this method is that commercial metal deposition tools do not allow the metal atoms to be deposited exclusively from a vertical direction. Metal ions that are sputtered or evaporated enter the lift-off stencil openings at various angles to the normal. This often results in undesired metal deposited along the inner walls of the lift-off structure, a problem known as "footing". While some footing is tolerable for line widths greater than one micron, it can lead to difficult lift-off and electrical shorts in the integrated circuit for line widths less than one micron.